The present invention relates to flash memories and, more particularly, to a method of using a flash memory. Flash memory cells can be programmed with either one bit per cell or more than one bit cell. In particular, the present invention is based on causing a flash device storing more than one bit per cell to emulate the behavior and reliability characteristics during booting of a flash device storing one bit per cell.
Flash memory devices have been known for many years. Typically, each memory cell within a flash memory stores one bit of information. The traditional way to store a bit in a flash memory cell has been by supporting two states of the cell. One state represents a logical “0” and the other state represents a logical “1”. In a flash memory cell, the two states are implemented by having a floating gate above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within the floating gate. Typically, one state is with zero charge in the floating gate and is the unwritten state of the cell after being erased (commonly defined to represent the “1” state) and the other state is with some amount of negative charge in the floating gate (commonly defined to represent the “0” state). Having negative charge in the gate causes the threshold voltage of the cell's transistor (i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct) to increase. It is possible to read the stored bit by checking the threshold voltage of the cell. If the threshold voltage is in the higher state then the bit value is “0” and if the threshold voltage is in the lower state then the bit value is “1”. Actually there is no need to accurately read the cell's threshold voltage. All that is needed is to correctly identify in which of the two states the cell is currently located. For this purpose it is sufficient to compare the threshold voltage of the cell to a reference voltage that is between the two states, and to determine if the cell's threshold voltage is below or above the reference value.
FIG. 1A (prior art) shows graphically how this works. Specifically, FIG. 1A shows a distribution of the threshold voltages of a large population of cells. Because the cells in a flash device are not exactly identical in their characteristics and behavior (due to, for example, small variations in impurity concentrations or defects in the silicon structure), applying the same programming operation to all the cells does not cause all the cells to have exactly the same threshold voltage. Instead, the threshold voltage is distributed as shown in FIG. 1A. Cells storing a value of “1” typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the central voltage value of the left peak (labeled 1) of FIG. 1A, with fewer cells having threshold voltages lower or higher than the central voltage of the left peak. Similarly, cells storing a value of “0” typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the central voltage of the right peak (labeled 0) of FIG. 1A, with fewer cells having threshold voltages lower or higher than the central voltage of the right peak.
In recent years, a new kind of flash device has appeared on the market, using “Multi Level Cells” (MLC). The term “Multi-Level Cell” is misleading because flash memory with a single bit per cell uses multiple i.e. two levels, as described above. Therefore, the term “Single Bit Cell” (SBC) is used hereinafter to refer to a memory cell of two levels and the term “Multi-Bit Cell” (MBC) is used hereinafter to refer to a memory cell of more than two levels, i.e. more than one bit per cell. The present discussion is directed primarily to an MBC flash memory with two bits per cell. It should however be understood that the present invention is equally applicable to flash memory devices that support more than two bits per cell.
A single MBC cell storing two bits of information is in one of four different states. As the cell's “state” is represented by the cell's threshold voltage, an MBC cell supports four different valid ranges for the cell's threshold voltage. FIG. 1B (prior art) shows the threshold voltage distribution for a typical MBC cell of two bits per cell. As expected, FIG. 1B has four peaks, each peak corresponding to one state. As for the SBC, each state is actually a voltage range and not a single voltage. When reading the cell's contents, the cell's threshold voltage must be correctly identified in a definite voltage range. For a prior art example of an MBC flash device see U.S. Pat. No. 5,434,825 to Harari.
A cell designed for MBC operation e.g. in four states is typically operable as an SBC cell with two states. For example, Conley et al. in U.S. Pat. No. 6,426,893 incorporated by reference for all purposes as if fully set forth herein, disclosed using both MBC and SBC modes within the same device, selecting certain parts of the device to operate with highest density in MBC mode, while other parts are used in SBC mode to provide better performance.
MBC devices provide a significant cost advantage. An MBC device with two bits per cell requires about half the area of a silicon wafer than an SBC of similar capacity. However, there are drawbacks to using MBC flash. Average read and write times of MBC memories are longer than of SBC memories, resulting in worse performance. Also, the reliability of MBC is lower than SBC. The difference between the threshold voltage ranges in MBC are much smaller than in SBC. Thus, a disturbance in the threshold voltage (e.g. leakage of stored charge causing a threshold voltage drift or interference from operating neighboring cells) that are insignificant in SBC because of the large gap between the two states, may cause an MBC cell to move from one state to another, resulting in an erroneous bit. The end result is a lower performance specification of MBC cells in terms of data retention time or the endurance of the device to many write/erase cycles.
Another ramification of the lower reliability of MBC devices compared to SBC devices is the required level of error correction. Manufacturers of SBC NAND flash devices typically advise users to apply an Error Correction Code (ECC) capable of correcting 1 bit error in each page of 512 bytes of data. But data sheets of MBC NAND flash devices typically advise applying an ECC capable of correcting 4 bit errors in each page of 512 bytes of data. For pages of size 2048 bytes such as in the case of NAND devices known as “large block devices”, the suggestion is to apply error correction per each portion of 512 bytes of the page. The present invention applies to all types of flash devices, regardless of page size. In this application the term “N-bit ECC” refers to an ECC scheme capable of correcting N bit errors in 512 bytes of data, if the 512 bytes are the size of one page, less than one page, or more than one page.
NAND flash devices are non-executable. Code execution requires random access in the sense that each byte is immediately accessible to the processor of the system independently of any other byte. NAND flash devices do not fully support random access as required for code execution. Instead, NAND devices support only serial access within a page, so that a processor has to first instruct the flash device to load a specified page from the storage array into a device-internal buffer, and then the contents of the buffer are serially shifted out of the flash device. NAND flash devices do not support directly executing a processor's code, e.g. boot code for booting an operating system. In order to use NAND flash memory devices for storing the boot code, there are different approaches. A common approach is to copy or “shadow” the boot code from the flash device into another type of memory, e.g. volatile RAM that is directly executable. Shadowing the boot code provides a solution for executing the shadowed boot code; but how is the shadowing performed? The boot code stored in non-executable memory cannot copy itself for instance into RAM! There are several approaches for executing the booting code. One approach is to have the boot code stored in a separate device that does support direct execution. The separate device may be an EEPROM NOR flash, or a ROM embedded within the CPU. In these cases, the boot code starts to run from executable memory. The boot code copies additional code from the non-executable flash memory to RAM, and then performs a jump into the additional code and continues with system initialization tasks. A second approach for executing boot code uses non-volatile memory and employs a hardware-supported mechanism that upon power-up automatically copies the contents of a previously-defined portion of the flash memory into executable memory, and system hardware is configured to start execution from the executable memory. The second approach is used with the hardware-supported mechanism implemented either within the flash device (as is the case in the DiskOnChip™ flash devices manufactured and sold by M-Systems of Kfar-Saba, Israel), or within the processor of the system (as is the case with some of the OMAP processors manufactured and sold by Texas Instruments).
Executable code compared with other types of data are relatively intolerant to bit errors. A single bit error in executable code of a processor might turn a processor command into a completely different command, changing the flow of the program, and most probably rendering the program useless. Therefore, there is a requirement to insure the code read from the flash device to the system's processor for execution is provided without errors.
There are several approaches to insure error-free execution of boot code stored in a non-executable non-volatile memory. One approach uses circuitry either integrated within the memory die or in a memory controller logically attached to the memory die, and relies on using redundancy to store the code. For example, four independent copies of the boot code are stored in the non-volatile memory. The automatic-loading hardware mechanism responsible for shadowing the boot code to executable memory has circuitry for Error Detection Coding (EDC) that enables the hardware mechanism to detect the bit errors in the shadowed code. Alternatively, circuitry for ECC in the loading mechanism may be used, however, ECC in the loading mechanism is typically avoided so as to reduce hardware complexity and cost. If the EDC circuitry detects errors in the code during shadowing, the EDC circuit without the processor's involvement discards the erroneous copy of the code and instead loads the second copy. Again, if errors are detected while copying the second copy, the second copy is also discarded and the third copy is used. All four copies are tried. The probability that all four copies will turn out to be erroneous is very small. This approach used by the M-Systems' DiskOnChip™ devices, suffices for assuring a reliable system boot.
A second approach to insure reliability of the boot code includes a hardware flash controller typically embedded in the processor that is configured, upon power-up, to automatically read the boot code from a previously determined address in the non-volatile memory (usually address zero) into an executable memory embedded within the controller. The controller includes not only EDC circuitry for detecting bit errors in the code, but also ECC circuitry for correcting them. This is the more common approach in current generation processors targeted for the mobile phones market, as for example in Texas Instruments' OMAP 1710 processor.
When processors of the current generation were designed, MBC NAND flash devices were not very common in the market and SBC devices were the norm. Therefore, designs of current processors ignore unique considerations of MBC devices. As typical SBC NAND devices are specified to guarantee no more than one bit error per 512 bytes, the flash controller of those processors is provided with ECC circuitry capable of correcting one error per 512 bytes. If the shadowed boot code happens to have more than one bit error in any 512-bytes section, sufficient error correction might not take place, and the system may not boot. Although MBC and SBC NAND devices have very similar electrical and logical interface, it is still not practical to boot the system from an MBC device, since the MBC device does not guarantee a sufficiently low number of errors to guarantee successful boot. As mentioned above, typical MBC NAND devices are specified to four bit errors per 512 bytes. Therefore, if an MBC NAND device is connected to the processor for providing the boot code, the MBC NAND device might have up to 4 bit errors in the first boot sector of 512 bytes. The processor's flash controller, even if able to detect the errors, will not be able to correct them, resulting in an attempt to execute erroneous boot code, most probably resulting in lock-up causing a hanging cellular phone, or digital camera.
Although MBC NAND is a mature technology and available in mass production lots, MBC NAND technology cannot be used by many processors in the market, even though the technology otherwise satisfies most system requirements. This is a major drawback since MBC devices require less space on the silicon wafer compared with SBC devices of similar storage capacity and hence MBC devices provide a major cost reduction.
There is thus a need for, and it would be highly advantageous to have, a way of utilizing MBC flash technology with current processors.